Responsibility:
· Design radio transceiver blocks, such as PA, LNA, mixer, TIA, LPF, VGA, ADC/DAC, etc.
· Design LO blocks, such as crystal oscillator, RF synthesizer, LO distribution network.
· Design Analog blocks, such as Bandgap, POR, LDO, DC-DC converter, Low power clock, power detector, ESD, test mux, etc.
· Guide layouts engineer to do the layout, and able to do the critical layout individually with DRC/LVS/xRC.
· Work with the team to define the block specs, doing link budget analysis, noise, linearity, phase noise, SNR, and EVM optimization.
· Work with the team on RC calibration, VCO calibration, IQ calibration, DC offset calibration, DPD, etc.
· Perform mix signal verification using AMS, Verilog, and system Verilog.
· Perform RF/analog and digital layout integration.
· Write test plans, perform design verification, and ATE production support.
Qualification:
· Master's or Ph.D. in electrical engineering.
· Typically requires 5+ years of RF/Analog and mixed-signal design experience.
· Experience in WiFi, BLE, or cellular chip design.
· Familiar with wireless communication theory
· Familiar with Cadence design tools for simulation and layout.
· Familiar with EM simulation using EMX/HFSS/ADS.
· Familiar with Link budget analysis, noise linearity, and phase noise analysis.
· Familiar with CMOS or SOI on deep submicron or FinFet technology to design circuits.
· Familiar with chip verification in the lab, using the network analyzer, spectrum analyzer, LitePoint, signal analyzer, etc.
· Using Verilog, system Verilog, Python, Matlab, and C, etc.
· Good documentation and communication skills.
Basic qualifications:
BSEE is required, MSEE/Ph D. in Electrical Engineering with desired experiences in wireless SoC ASIC design and verification is preferred.
Responsibilities:
You will work with different teams on a WLAN ASIC chip product development project. In this role, you will be performing the following tasks:
Develop WLAN chip architecture and micro-architecture designs with architects, system or algorithm teams
RTL design and implementations of SoC modules from spec to tape out
Develop and perform required ASIC design flows and methodologies for the WLAN ASIC product
Work with verification team to develop SoC level test cases and test coverage
Perform silicon lab bring up and test
ASIC product power, performance and area optimizations
Required Skills:
Strong skills in Verilog and digital logic designs at RTL level
Strong skills with ASIC design flows and methodologies
Detailed knowledge of interconnect buses like AMBA AXI, AHB, and APB. Strong experience with Synopsys core consultant or ARM NIC-400
Detailed knowledge of ARM CPUs like Cortex-R and Cortex-M
Detailed knowledge of SRAM or DDR memory controller designs
Direct experiences with ASIC IPs like PCIs, USB, Ethernet
Direct hands-on experiences with FIFO, DMA and SRAM arbiter designs
Direct hands-on experiences with FIFO, DMA, and SRAM arbiter designs
Strong experiences in a major scripting language like Perl/Tcl/Python
Strong knowledge and working experiences with backend design teams in P&R layout designs, floorplanning, pin-mux design and timing closures
Proven track records of delivering complex ASIC product in mass production
Experiences in Wi-Fi, Bluetooth, networking designs are definitely a plus
Responsibilities
· Work with system/Algorithm team to define baseband requirements.
· Design micro-architecture based on system specification.
· Implement RTL codes of digital blocks and Baseband level integration in Verilog from specification to functional module and baseband top.
· Verify module level functionality and system integration through simulation in verification environment.
· Generate design document and conduct design review with internal teams.
· Support verification regression and debugging at module level and system level.
· Optimize the design in Area and Power at various development stages.
· Support Synthesis and Backend for timing closure.
Qualifications:
MS in EE, Computer Engineering, and relevant fields
Experience requirements:
Entry level position with 0-2 years of experience
Senior and above level positions with a minimum of 2 years of experience
Basic understanding of communications/DSP algorithms, and IEEE802.11 PHY standards.
Ability to design micro-architecture for computational modules and FSM for control modules.
Good experience in RTL coding in Verilog, building simple verification environment, and trouble-shooting for correct functionality.
Understanding of synthesis and timing closure requirements.
Ability to optimize the design for balanced PPA.
Basic qualifications:
BSEE is required, MSEE/Ph D. in Electrical Engineering with desired experiences in wireless SoC ASIC design and verification is preferred.
Responsibilities:
You will work with different teams on a WLAN ASIC chip product development project. In this role, you will be performing the following tasks:
Develop MAC layer micro-architecture designs with architects, system or algorithm teams
RTL implementations of MAC layer modules from spec to tape out
Perform required ASIC design flows and methodologies in the MAC designs
Work with verification team to develop test cases and test coverage
Perform silicon lab bring up and test
MAC layer design power, performance and area optimizations
Required Skills:
Strong skills in Verilog and digital logic designs at RTL level
Strong skills with ASIC design flows and methodologies
Detailed knowledge of Wi-Fi 802.11 a/b/g/n/ac/ax/be MAC protocols and standards
Highly experienced with Wi-Fi MAC layer packet processing hardware module designs including aggregation/de-aggregation, segmentation/de-segmentation, and frame packing
Highly experienced with MAC layer control hardware module designs include scheduling, rate control, sounding, TX vector and RX vector calculations, re-ordering, acknowledgement, and re-transmit controls
Direct experiences with WEP/TKIP/AES or other major encryption standards.
Direct hands-on experiences with FIFO, DMA, and SRAM arbiter designs
Direct hands-on experience with Buffer Management and Queue Management designs
Strong experiences in a major scrypting language like Perl/Tcl/Python
Strong knowledge and working experiences with backend design teams in P&R layout designs and timing closures
Experiences working with ARM CPUs like Cortex-R and Cortex-M
Proven track records of delivering designs in complex ASIC product mass production
Experiences in Bluetooth, networking designs are definitely a plus
Qualifications:
· MS or higher degree in EE, CS or related fields,
· Experience requirements:
o Entry level positions: 0-2 years of experience
o Senior and above level positions: a minimum of 2 years of experience
· Proficiency in System Verilog, Object Oriented Programming, Scripting Languages
· Experience in UVM development
· Detailed understanding of UVM methodology, flows and test-bench structures
· Basic understanding of IEEE802.11 PHY and MAC standard
· Experience in debugging designs of IP level (Wi-Fi Baseband, and MAC) or SOC level
· Good communication and documentation skills
Responsibilities:
· Work with system architects, algorithm engineers, and RTL designers to define Wi-Fi AP chip verification requirements.
· Architect and build IP and system UVM verification environments.
· Create IP and system verification coverage plans, and generate test cases, based on the specification and review the plan with system architects and design engineers
· Report failures, participate in the debugging with various teams, and track bugs
· Conduct verification regressions, analyze the results, and review with design teams
· Develop verification flows for code coverage and functional coverage for Baseband, MAC, and SOC
Looking for a key member of the Wi-Fi host driver team where you will be working on Linux programming, testing and optimization from early prototypes till productization. You will also be working across multiple software stacks (GNU Open Sources and propriety drivers) to implement features with the hardware and software teams collaboratively.
The work involves devising performance evaluation methodologies on the products and making an improvement of software design to achieve the expected throughput on Wi-Fi connectivity.
Key Qualifications:
· Prior experience and proven skill of embedded Linux programming for Wi-Fi driver SW development is a must.
Knowledge and experience of OpenWRT, hostapd and WPA3 are highly preferred.
· Linux kernel networking stack knowledge and understanding of operating system fundamentals.
Strong competence and experience in Layer 2, Layer 3 networking optimization with XDP or DPDK are required.
· Experience developing software for BSP, boot loader, coredump is a plus.
· Experience of participation in the complete life cycle of product(s) is a big plus.
· Good communications skills and a teamwork spirit are required.
Education & Experience:
· Bachelor’s degree in computer science or equivalent, master’s degree is preferred.
· 5+ years of relevant industry experience.
· 3+ years of Wi-Fi driver SW experience is required.
Qualifications
• PhD or MS (with 2+ years of experience), in EE or relevant fields.
• Solid background in digital communications, digital signal processing, and error control codes.
• Experience in wireless system and algorithm developments in WLAN and cellular systems, and understanding of OFDM, OFDMA, SU/MU-MIMO, beamforming.
• Ability to learn new technologies quickly.
• Ability to conduct simulations in Matlab and C++ to evaluate the performance of various algorithms in fixed point format, and make overall system performance tradeoffs.
• Ability to define system requirements and provide detailed system spec and fixed point models to design team, and verification team.
• Experience in system performance tuning and issue investigation.
• Good communication skills and documentation capability.
Responsibilities
• Responsible for WLAN system definition and performance specification.
• Conducting competition analysis.
• Responsible for WLAN algorithm development, fixed point optimization, overall system performance evaluation.
• Responsible for system simulation development and maintenance.
• Providing detailed fixed point spec, system operation requirements, and verification references.
• Working with other teams on chip bring-up, trouble-shooting, performance tuning, new SW feature development, and system level issue investigation.
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